Provide code paths for pre-ARMv6t2 ARM ISAs.

objc_msgSend.arm.S

@@ -1,5 +1,28 @@
 .syntax unified
 .fpu neon
+#if ((__ARM_ARCH >= 7) || defined (__ARM_ARCH_6T2__))
+.macro byte1 dst, src
+	uxtb   \dst, \src
+.endm
+.macro byte2 dst, src
+	ubfx   \dst, \src, #8, #8
+.endm
+.macro byte3 dst, src
+	ubfx   \dst, \src, #16, #8
+.endm
+#else
+.macro byte1 dst, src
+	and \dst, \src, #0xff
+.endm
+.macro byte2 dst, src
+	and \dst, \src, #0xff00
+	lsr \dst, \dst, 8
+.endm
+.macro byte3 dst, src
+	and \dst, \src, #0xff00
+	lsr \dst, \dst, 16
+.endm
+#endif
 
 // Macro for testing: logs a register value to standard error
 .macro LOG reg
@@ -38,15 +61,15 @@
 	teq    r6, #0
 	beq    2f
 
-	ubfx   r6, r5, #16, #8                // Put byte 3 of the sel id in r6
+	byte3  r6, r5                         // Put byte 3 of the sel id in r6
 	add    r6, r4, r6, lsl #2             // r6 = dtable address + dtable data offset
 	ldr    r4, [r6, #DATA_OFFSET]         // Load, adding in the data offset
 1:                                        // dtable16
-	ubfx   r6, r5, #8, #8                 // Put byte 2 of the sel id in r6
+	byte2  r6, r5                         // Put byte 2 of the sel id in r6
 	add    r6, r4, r6, lsl #2             // r6 = dtable address + dtable data offset
 	ldr    r4, [r6, #DATA_OFFSET]         // Load, adding in the data offset
 2:                                        // dtable8
-	uxtb   r6, r5                         // Low byte of sel id into r5
+	byte1  r6, r5                         // Low byte of sel id into r5
 	add    r6, r4, r6, lsl #2             // r6 = dtable address + dtable data offset
 	ldr    ip, [r6, #DATA_OFFSET]         // Load, adding in the data offset