* Implement PowerPC block trampoline
* Adjust pagesize on ppc64
* Skip UnexpectedException test for PowerPC
* Move PAGE_SIZE to asmconstants.h
* Use PAGE_SIZE and PAGE_SHIFT macros for PowerPC
* Add ppc64el and powerpc qemu-crossbuild targets
* Add NO_SAFE_CACHING definition and guards
* Do not export objc_method_cache_version on ppc32
---------
Co-authored-by: David Chisnall <davidchisnall@users.noreply.github.com>
* RISC-V objc_msgSend implementation
* Use objc_msgSend.riscv64.S if requirements are met
* RISC-V 64-bit block trampoline
* Fix formatting
* Add riscv64 crossbuild in CI
* Exclude llvm 13 and 14 for riscv64 in CI
* Add RISC-V and Windows on ARM to ANNOUNCE
* Add comment to why we exclude architectures in qemu-crossbuild
* Remove duplicated entry in ANNOUNCE
This change is effectively a no-op (it's impossible to throw an
exception through these trampolines, because they tail call the real
block), but it does prevent the linker from complaining that we're
linking SEH-aware and SEH-unaware code.
Hugo Melder
Rupert Daniel
David Chisnall
David Chisnall
David Chisnall
theraven
ericwa